1. Field of the Invention
This invention relates to the formation of microelectronic circuits and, more specifically, to the method of forming interconnection regions on a substrate and the method of fabricating the microelectronic circuit.
2. Brief Description of the Art
Interconnect top metal systems for use in conjunction with the formation of multicomponent modules (MCMs) have generally been limited to a single metal finish. Printed circuit boards typically provide either copper, tin/lead solder, tin/nickel or gold. Military and high reliability circuits usually insist on gold as a finish surface over a nickel barrier and a chromium adhesion layer. Commercial multicomponent modules use aluminum as the thin film conductor and usually leave the aluminum as the pad metal to which gold wire bonds are stitched. Solder coated and gold coated pads are not generally produced on the same interconnect circuit board because fabrication costs are high and contamination of the gold pads with solder results in brittle gold-tin intermetallics that can be highly resistive.
In the packaging of bare semiconductor dice on interconnects by the technique known as MCM assembly, it is advantageous to be able to use tested dice that are known to be electrically sound and of known reliability. This assures the manufacturer of high yields and the customers of a reliable system. Reliable testing of individual die presently requires some form of bonding to a reusable lead frame, e.g., TAB or solder ball or C4 flip-chip bonding to a reusable test interconnect. These known good die (KGD) technologies are particularly suitable for systems requiring the highest reliability, i.e., military and space systems. When other techniques become available to provide KGD without additional processing, the bare die can be attached with the more traditional wire bonding techniques. In order to take advantage of these various joining techniques, bonding sites on the interconnect must be of the correct metallurgy. Presently, interconnect top metal systems provide metallurgical joints and dice for either TAB or flip-chip technologies, but both are not used on the same interconnect.
Flip-chip technology has been practiced by creating the solder bump on the die. No prior technology has provided solder bumps as high as 75 to 100 microns in diameter on an interconnect metal pad. Plating of solder is a means to provide bumps of this diameter. However, arrays of solder bumps plated in an irregular pattern on a field creates bumps of very non-uniform volume and composition.
Gold bumps on the die and interconnect are usually electro-plated. Although the plating baths are designed to control the grain size and the hardness of these bumps, the hardness is usually very variable and ranges too high. Thus, the bumps must be annealed after plating to reduce the hardness and the variability. If the flip-chip solder is to be placed on the interconnect along with gold bumps for TAB, the gold bumps must be annealed before the solder is deposited.
Small solder bumps can be deposited by evaporation of tin and lead through pre-aligned shadow masks. This is the method of choice as described by the prior art to deposit solder bumps on flip-chip dice, but is capital intensive and very costly. Also, the evaporation technique deposits the metal in a non-selective manner. The shadow masks collect the excess solder and must be cleaned after each evaporation run. This by-product stream is a hazardous waste that requires costly disposal. Cleaning after every deposition run requires duplicate shadow mask tooling and high labor cost for its maintenance.